Industrial control processor system
Variable architecture digital computer
Logically transportable microprocessor interface control unit permitting bus transfers with different but compatible other microprocessors
Coordinating speculative and committed state register source data and immediate source data in a processor
Idiom recognizer within a register alias table
Floating point register alias table FXCH and retirement floating point register array
Exception handling circuit and method
Integer and floating point register alias table within processor device
Speculative and committed resource files in an out-of-order processor
Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer
ApplicationNo. 052994 filed on 03/31/1998
US Classes:712/208INSTRUCTION DECODING (E.G., BY MICROINSTRUCTION, START ADDRESS GENERATOR, HARDWIRED)
ExaminersPrimary: Eng, David Y.
Attorney, Agent or Firm
International ClassG06F 009/40
AbstractA method and apparatus for updating the architectural state in a system implementing staggered execution with multiple micro-instructions. According to one aspect of the invention, a method is provided in which a macro-instruction is decoded into a first and second micro-instructions. The macro-instruction designates an operation on a pieced of data, and execution of the first and second micro-instructions separately cause the operation to be performed on different parts of the piece of data. The method also requires that the first micro-instruction is executed irrespective of the second micro-instructions (e.g., at a different time), and that it is detected that said second micro-instruction will not cause any non-recoverable exceptions. The results of the first micro-instruction are then used to update the architectural state in an earlier clock cycle than said second micro-instruction.