Fast multiplier architecture
Recoded iterative multiplier
High speed parallel multiplication circuit having a reduced number of gate stages
Digital signal processor with delayed-evaluation array multipliers and low-power memory addressing
Booth array multiplying circuit having carry correction
Booth multiplier with high speed output circuitry
Multiplier circuit design for a programmable logic device Patent #: 5754459
AbstractA digital parallel multiplier having encoders for each segmented bit pair of the multiplier input data and which selects one of 4 coefficients, based on the sum of the bit pair, that are then applied to the multiplicand input data. When a 3X coefficient of the multiplicand input data is to be generated, a -1 coefficient is output by the encoder requiring the 3X coefficient, and a 1 is added to the sum of the next most significant bit pair.