IC with test cells having separate data and test paths
Patent 6081916 Issued on June 27, 2000. Estimated Expiration Date: 
March 25, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
March 25, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesInterleaved method and circuitry for testing for stuck open faults Logic function circuit with an array of data stores and their circuit testing Boundary scan cell Testing buffer/register Programmable scan chain testing structure and method Scan latch using half latches Patent #: 5719876 InventorAssigneeApplicationNo. 826310 filed on 03/25/1997US Classes:714/727Boundary scanExaminersPrimary: Nguyen, Hiep T.Attorney, Agent or FirmInternational ClassG01R 031/28AbstractA test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously. | |
