Patent ReferencesCache memory organization utilizing miss information holding registers to prevent lockup from cache misses Hierarchical packet scheduling method and apparatus Scheduler design for ATM switches, and its implementation in a distributed shared memory architecture Relative logarithmic time stamps for reduced memory map size Patent #: 5978928 InventorsAssigneeApplicationNo. 185755 filed on 11/04/1998US Classes:370/235, Flow control of data transmission through a network370/252, Determination of communication parameters370/392, Processing of address header for routing, per se370/412Queuing arrangementExaminersPrimary: Horabik, MichaelAssistant: Jones, Prenell Attorney, Agent or FirmInternational ClassG01R 031/08AbstractCompensating for time stamp aging in systems employing fair packet queuing algorithms by (i) representing a time stamp of each head-of-line packet of a session with a finite number of bits, (ii) representing a system potential with a finite number of bits, (iii) storing a packet's time stamp when it is served, (iv) storing an obsolete indicator for each stored time stamp, and (v) updating the obsolete indicator or purging obsolete time stamps. | |