Patent ReferencesInsulated-gate transistor having narrow-bandgap-source Process for fabricating a fully self-aligned soi mosfet MOS poly-si thin film transistor with a flattened channel interface and method of producing same Method for forming an ultra high density inverter using a stacked transistor arrangement Late process method for trench isolation Patent #: 5872044 InventorAssigneeApplicationNo. 130423 filed on 08/06/1998US Classes:438/151, Having insulated gate257/E23.105, Wire-like or pin-like cooling fins or heat sinks (EPO)438/152Combined with electrical device not on insulating substrate or layerExaminersPrimary: Nelms, David C.Assistant: Lebentritt, Michael S. Attorney, Agent or FirmInternational ClassH01L 021/00AbstractA heat sink is formed on a bonded semiconductor on insulator (SOI) wafer. A trench is formed which extends from a top of the bonded SOI wafer through an isolation region of the bonded SOI wafer to a base of the bonded SOI wafer. The base of the bonded SOI wafer is located below the isolation region of the bonded SOI wafer. A conductive pillar is formed in the trench. The conductive pillar extends from the top of the bonded SOI wafer through the isolation region of the bonded SOI wafer and is physically in contact with but electrically insulated from the base of the bonded SOI wafer. In the preferred embodiment, the conductive pillar is formed of doped polysilicon. The doped polysilicon is of a conductivity type which is different than the conductivity type of the base. Out-diffusion from the doped polysilicon forms a region within the base which electrically insulates the conductive pillar from the base. | |