U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Method and system for solving linear systems

Patent 6078938 Issued on June 20, 2000. Estimated Expiration Date: Icon_subject May 29, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3697703

3748451

Matrix multiplier in GF(2m)
Patent #: 4037093
Issued on: 07/19/1977
Inventor: Gregg ,   et al.

Heat exchanger tube ferrule
Patent #: 4156299
Issued on: 05/29/1979
Inventor: Kovac

Logarithmic conversion apparatus
Patent #: 4626825
Issued on: 12/02/1986
Inventor: Burleson ,   et al.

Finite element analysis method using multiprocessor for matrix manipulations with special handling of diagonal elements
Patent #: 4787057
Issued on: 11/22/1988
Inventor: Hammond

Calculator of matrix products
Patent #: 4914615
Issued on: 04/03/1990
Inventor: Karmarkar, et al.

Preconditioned conjugate gradient system
Patent #: 5136538
Issued on: 08/04/1992
Inventor: Karmarkar, et al.

Parallel processing computer for solving dense systems of linear equations by factoring rows, columns, and diagonal, inverting the diagonal, forward eliminating, and back substituting
Patent #: 5301342
Issued on: 04/05/1994
Inventor: Scott

Methods for using a processor array to perform matrix calculations
Patent #: 5319586
Issued on: 06/07/1994
Inventor: Gupta, et al.

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Inventors

Assignee

Application

No. 657471 filed on 05/29/1996

US Classes:

708/500, Evaluation of root708/501, Multiplication followed by addition708/502Reciprocal

Examiners

Primary: Auve, Glenn A.
Assistant: Vo, Tim

Attorney, Agent or Firm

Foreign Patent References

  • WO 93/17383 WO 09/13/1993

International Class

G06F 001/02

Abstract

A system and method of using a computer processor (34) to generate a solution to a linear system of equations is provided. The computer processor (34) executes a Jacobi iterative technique to produce outputs representing the solution. Multiplication operations required by the iterative technique are performed using logarithmic arithmetic. With logarithmic arithmetic, a multiplication operation is accomplished using addition. For a given n×n matrix A, the computer processor (34) can compute an inverse matrix A-1 by repeatedly executing the iterative technique to solve n linear systems.

Other References

  • Numerical Analysis Fifth Edition, Richard L. Burden et al., PWS Publishing Company, 1993, pp. 406-411
  • Table-Look Algorithms for Elementary Functions and Their Error Analysis, Ping Tak Peter Tang, Proceedings of 10th Annual IEEE Symposium on Computer Arithmetic's, pp. 232-236, Jun. 1991
  • A 30-b Integrated Logarithmic Number System Processor, Lawrence K. Yu et al., IEEE Journal of Solid-State Circuits, vol. 26, No. 10, Oct. 1991, pp. 1433-1440
  • An Architecture for Addition and Substraction of Long Word Length Numbers in the Logarithmic Number System, David M. Lewis, IEEE Transactions on Computers, vol. 39, No. 11, Nov. 1990, pp. 1325-1336
  • Algorithmic Design for a 30 bit Integrated Logarithmic Processor, David M. Lewis et al., Proceedings on 9th Symposium on Computer Arithmetic, 1989, IEEE Comp. Soc. Press, pp. 192-199
  • A Multiplier-Less Digital Neural Network, L. Spaanenburg et al., Proceedings of the 2nd International Conference on Microelectronics for Neural Networks, German Section of the Institute of Electrical and Electronics Engineers, Published by Kyrill & Method Verlag, Oct. 16-18, 1991
  • A Logarithmic Vector Processor for Neural Net Applications, Steve Richfield, IEEE First International Conference on Neural Networks, Jun. 21-24, 1987, pp. 22-28
  • Comments on An Architecture for Addition and Substraction of Long Word Length Numbers in the Logarithmic Number System, M. Arnold et al., IEEE Transactions on Computers, vol. 41, No. 6, 1992, pp. 786-788
  • Redundant Logarithmic Arithmetic, Mark G. Arnold et al., IEEE Transactions on Computers, vol. 39, No. 8, Aug. 1990, pp. 1077-1086
  • Redundant Logarithmic Number Systems, M.G. Arnold et al., Proceedings of 9th Symposium on Computer Arithmetic, 1989, IEEE Comp. Soc. Press, pp. 144-151
  • Improved Accuracy for Logarithmic Addition In DSP Applications, Mark G. Arnold et al., ICASSP 88: International Conference of Acoustics, Speech and Signal Processing, Published IEEE, pp. 1714-1717, vol. 3
  • Applying Features of IEEE 754 to Sign/Logarithm Arithmetic, Mark G. Arnold et al., IEEE Transactions on Computers, vol. 41, No. 8, Aug. 1992, pp. 1040-1050
  • An Accurate LNS Arithmetic Unit Using Interleaved Memory Function Interpolar, David M. Lewis, Proceedings of 11th Symposium on Computer Architecture, 1993, IEEE Comp. Soc. Press, pp. 2-9
  • Interleaved Memory Function Interpolars with Application to an Accurate LNS Arithmetic Unit, David M. Lewis, IEEE Transactions on Computers, vol. 43, No. 8, Aug. 1994, pp. 974-982
  • A 10-ns Hybrid Number System Data Execution Unit for Digital Signal Processing Systems, Fang-shi Lai, IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, pp. 590-598
  • A Hybrid Number System Processor with Geormetric and Complex Arithmetic Capabilities, Fang-shi Lai et al., IEEE Transactions on Computers, vol. 40, No. 8, Aug. 1991, pp. 952-961
  • The Efficient Implementation and Analysis of a Hybrid Number System Processor, Fang-shi Lai, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 40, No. 6, Jun. 1993, pp. 382-39
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