U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Timing synchronization and switchover in a network switch

Patent 6078595 Issued on June 20, 2000. Estimated Expiration Date: Icon_subject August 28, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Apparatus and method for clock alignment and switching
Patent #: 5515403
Issued on: 05/07/1996
Inventor: Sloan, et al.

Method and system for aligning the phase of high speed clocks in telecommunications systems
Patent #: 5638410
Issued on: 06/10/1997
Inventor: Kuddes

Phase locked loop using a counter and a microcontroller to produce VCXO control signals Patent #: 5726607
Issued on: 03/10/1998
Inventor: Brede, et al.

Inventors

Assignee

Application

No. 920250 filed on 08/28/1997

US Classes:

370/503, Synchronizing370/219Standby switch

Examiners

Primary: Pham, Chi
Assistant: Nguyen, Khiem

Attorney, Agent or Firm

International Class

H04J 003/06

Abstract

A data communications switch and method of operation are presently disclosed enabling flexible, selectable provision of a common timing signal for synchronized external communication through physical layer interfaces with other network devices, synchronized internal communications within the switch, and for uninterrupted synchronization of such communications. Synchronization of external communications is enabled by programmable selection from among plural potential timing references at redundant timing modules (TMs). An active TM provides a primary external synchronization clock; a standby TM provides a redundant timing function. Both TMs access the same references. A state signal indicates which synchronization clock is active. External interfaces derive timing from this distributed clock. Synchronized internal timing is provided by an internal clock and phase-locked loop (PLL) on each TM. The clock/PLL timing signal output is routed to other switch elements, enabling synchronized internal data transfer. Both interconnected TMs actively generate clock signals for external and internal use, enabling seamless timing switchover should conditions warrant a change in TMs.

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