DQPSK mapping circuit
Patent 6075827 Issued on June 13, 2000. Estimated Expiration Date: 
October 6, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
October 6, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesQuadrature phase signal processor Method and apparatus for encoding and decoding data Patent #: 5717394 InventorsAssigneeApplicationNo. 944510 filed on 10/06/1997US Classes:375/331, More than two phases329/310Including logic element (e.g., logic gate or flip-flop)ExaminersPrimary: Pham, ChiAssistant: Corrielus, Jean B. Attorney, Agent or FirmForeign Patent References
International ClassesH03D 003/22H04L 027/22 Foreign Application Priority Data1996-10-04 JPAbstractA DQPSK mapping circuit is disclosed which comprises: a parallel decoding circuit having inputs for decoding first to 2Nth bits of input data and one symbol period prior I and Q data which are prior by one symbol period from the present decoding cycle thereof through the inputs and outputting serial first to Nth I and Q data of the present decoding period in parallel, N is a natural number; and a FF circuit for supplying the Nth I and Q data to the inputs as the one symbol period prior I and Q data in the succeeding decoding cycle of the parallel decoding circuit. The parallel decoding circuit may comprise first to Nth decoders, an Mth decoder out of the first to Nth decoders decoding 2Mth bit and (2M-1)th bits of the input data and outputs of (M-1)th decoder, M being a natural number and MࣘN, wherein the first decoder decodes the one symbol period prior I and Q data and the first and second bits of the input data.Field of SearchSYSTEMS USING ALTERNATING OR PULSATING CURRENTQuadrature amplitude modulation With phase or frequency shift keying Phase shift keying Biphase (manchester codes) Phase shift keying Differential (diphase) More than two phases Plural phase (>2) Biphase (manchester code) Maximum likelihood decoder or viterbi decoder Particular pulse demodulator or detector PHASE SHIFT KEYING OR QUADRATURE AMPLITUDE DEMODULATOR Including logic element (e.g., logic gate or flip-flop Including logic element (e.g., logic gate or flip-flop) Serial to parallel | |
