Patent ReferencesMethod for detecting errors in models through restriction Patent #: 5946481 InventorsAssigneeApplicationNo. 042373 filed on 03/13/1998US Classes:703/13SIMULATING ELECTRONIC DEVICE OR ELECTRICAL SYSTEMExaminersPrimary: Teska, Kevin J.Assistant: Knox, Lonnie A. Attorney, Agent or FirmInternational ClassesG06F 017/50G06F 011/263 AbstractA method is provided for automatically enhancing verification of a design under test by using model checking on the state transitions captured during simulation. The enhanced verification is due to the fact that even though to all of the individual transitions captured were exercised during simulation, not all possible sequences of those transitions were necessarily exercised during the simulation, and the unexercised sequences may hide "bugs". The non-deterministic and exhaustive nature of the model checker ensures that all possible sequences comprising the captured state transitions are exercised. The methodology consists of utilizing the state transitions, and the inputs causing those state transitions as observed during simulation, to define legitimate input values that can be applied, nondeterministically and exhaustively, by the model checker to the design under test.Field of SearchSIMULATING ELECTRONIC DEVICE OR ELECTRICAL SYSTEM | |