Patent ReferencesMethod for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias Method for patterning metal oxide thin film Method for fabricating semiconductor device with interconnections buried in trenches High aspect ratio low resistivity lines/vias with a tungsten-germanium alloy hard cap Method of making a damascene metallization Method for using ammonium salt slurries for chemical mechanical polishing (CMP) Dual damascene process Copper chemical mechanical polishing slurry utilizing a chromate oxidant Chemical mechanical polishing (CMP) slurry for polishing copper interconnects which use tantalum-based barrier layers Method of forming dual damascene structure InventorsApplicationNo. 339085 filed on 06/23/1999US Classes:438/633, Simultaneously by chemical and mechanical means257/E21.3, Post treatment (EPO)257/E21.304, By chemical mechanical polishing (CMP) (EPO)257/E21.584, Barrier, adhesion or liner layer (EPO)438/624, Separating insulating layer is laminate or composite of plural insulating materials438/672, Plug formation (i.e., in viahole)438/687Copper of copper alloy conductorExaminersPrimary: Smith, MatthewAssistant: Rocchegiani, Renzo N. Attorney, Agent or FirmInternational ClassH01L 021/476.3AbstractA method of passivating copper interconnects is disclosed. A freshly electrodeposited copper interconnect such as formed as via/trench structures in semiconductor manufacturing is chemically converted to passivating surface of copper tungstate or copper chromate either through MOCVD reaction with vapors of tungsten or chromium alkoxides, or by pyrolytic reaction with tungsten or chromium carbonyl in the presence of O2. The copper interconnect having the formed passivation service is then chemically mechanically polished. The process can be used with various manufacturing processes, including single and dual damascene processes. | |