Digital event input circuit for a computer based process control system
Static memory allocation system
Bus event monitor
System independent interface for performance counters
Apparatus for monitoring the performance of a microprocessor
Apparatus and method for tracking events in a microprocessor that can retire more than one instruction during a clock cycle Patent #: 5881224
ApplicationNo. 980732 filed on 12/01/1997
US Classes:713/502Counting, scheduling, or event timing
ExaminersPrimary: Heckler, Thomas M.
Attorney, Agent or Firm
Foreign Patent References
International ClassG06F 011/30
AbstractA system and method for efficiently managing the primary memory of a processing system such as a general purpose computer system or a telecommunications network by increasing the amount of primary memory available for subscriber allocation through the use of a general purpose counters block (GPCB). The GPCB is divided into an event-map block that assigns event detectors to counters, an event-instructor block which activates the event detectors, an event-indication receiver for receiving signals from the event detectors, an assign/counter that activates general purpose counters, and general purpose counters for incrementing, storing and reporting event count information. The system also provides for designating the general purpose counters to monitor selected events in programs. The events can be monitored on an individual basis or in groups. In addition, a user interface is provided that uses an event-type selector to pick the events the system operator wishes to monitor, and a subscriber selector for indicating which subscribers should be monitored to see if a selected event occurs. The user interface includes a counter report which receives error messages from the counters and reports the errors to the operator terminal.
Field of SearchCounting, scheduling, or event timing