Semiconductor memory device having multilayer group IV nanocrystal quantum dot floating gate and method of manufacturing the same
Patent 6060743 Issued on May 9, 2000. Estimated Expiration Date: 
May 20, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
May 20, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSemiconductor element and semiconductor memory device using the same Quantum memory Electronic device Semiconductor device and a single electron device Nano-structure memory device Collective element of quantum boxes Single electron tunnel device and method for fabricating the same Non-volatile memory device Quantum box information storage device Patent #: 5905273 InventorsApplicationNo. 082613 filed on 05/20/1998US Classes:257/321, With thin insulator region for charging or discharging floating electrode by quantum mechanical tunneling257/9, THIN ACTIVE PHYSICAL LAYER WHICH IS (1) AN ACTIVE POTENTIAL WELL LAYER THIN ENOUGH TO ESTABLISH DISCRETE QUANTUM ENERGY LEVELS OR (2) AN ACTIVE BARRIER LAYER THIN ENOUGH TO PERMIT QUANTUM MECHANICAL TUNNELING OR (3) AN ACTIVE LAYER THIN ENOUGH TO PERMIT CARRIER TRANSMISSION WITH SUBSTANTIALLY NO SCATTERING (E.G., SUPERLATTICE QUANTUM WELL, OR BALLISTIC TRANSPORT DEVICE)257/12, Heterojunction257/14, Quantum well257/15, Superlattice257/17, With particular barrier dimension257/20, Field effect device257/24, Field effect device257/30, Tunneling through region of reduced conductivity257/314, Variable threshold (e.g., floating gate memory device)257/315, With floating gate electrode257/317, With irregularities on electrode to facilitate charging or discharging of floating electrode257/E29.301, Programmable by two single electrons (EPO)257/E29.304, Charging by tunneling of carriers (e.g., Fowler-Nordheim tunneling) (EPO)438/197, Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.)438/201, Including insulated gate field effect transistor having gate surrounded by dielectric (i.e., floating gate)438/257, Having additional gate electrode surrounded by dielectric (i.e., floating gate)438/264, Tunneling insulator438/962QUANTUM DOTS AND LINESExaminersPrimary: Hardy, David B.Assistant: Baumeister, Bradley Attorney, Agent or FirmForeign Patent References
International ClassesH01L 029/788H01L 029/06 H01L 029/15 H01L 021/336 Foreign Application Priority Data1997-05-21 JPAbstractThe semiconductor device comprises a first insulating layer formed on the semiconductor substrate, at least one double-deck semiconductor nanocrystal formed on the first insulating layer, the at least one double-deck semiconductor nanocrystal comprising a first semiconductor nanocrystal and a second semiconductor nanocrystal stacked one upon the other via a second insulating layer, and a third insulating layer selectively formed on the first insulating layer so as to cover the at least one double-deck semiconductor nanocrystal.Other References
Field of SearchTHIN ACTIVE PHYSICAL LAYER WHICH IS (1) AN ACTIVE POTENTIAL WELL LAYER THIN ENOUGH TO ESTABLISH DISCRETE QUANTUM ENERGY LEVELS OR (2) AN ACTIVE BARRIER LAYER THIN ENOUGH TO PERMIT QUANTUM MECHANICAL TUNNELING OR (3) AN ACTIVE LAYER THIN ENOUGH TO PERMIT CARRIER TRANSMISSION WITH SUBSTANTIALLY NO SCATTERING (E.G., SUPERLATTICE QUANTUM WELL, OR BALLISTIC TRANSPORT DEVICE)Heterojunction With particular barrier dimension Field effect device Current flow across well Field effect device Tunneling through region of reduced conductivity Quantum well Superlattice Variable threshold (e.g., floating gate memory device) With floating gate electrode With irregularities on electrode to facilitate charging or discharging of floating electrode With thin insulator region for charging or discharging floating electrode by quantum mechanical tunneling Multiple insulator layers (e.g., MNOS structure) Non-homogeneous composition insulator layer (e.g., graded composition layer or layer with inclusions) Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.) Including insulated gate field effect transistor having gate surrounded by dielectric (i.e., floating gate) Having additional gate electrode surrounded by dielectric (i.e., floating gate) Tunneling insulator Tunneling insulator QUANTUM DOTS AND LINES | |
