Computer system including a digital signal processor and conventional central processing unit having equal and uniform access to computer system resources
April 28, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMultiprocessor Real-time, concurrent, multifunction digital signal processor subsystem for personal computers Mechanism for implementing vector address pointer registers in system having parallel, on-chip DSP module and CPU core On-chip interface and DMA controller with interrupt functions for digital signal processor Apparatus and method for performing error correction in a multi-processor system System and method for transferring information between multiple buses Decoupled DMA transfer list storage technique for a peripheral resource controller Single chip multiprocessor architecture with internal task switching synchronization bus Method and apparatus for establishing host bus clock frequency and processor core clock ratios in a multi-processor computer system Method for reducing the number of coherency cycles within a directory-based cache coherency memory system uitilizing a memory state cache Patent #: 5809536 InventorsAssigneeApplicationNo. 846194 filed on 04/28/1997US Classes:712/35, Digital Signal processor710/240, ACCESS ARBITRATING712/28Distributed processing systemExaminersPrimary: Donaghue, Larry D.Attorney, Agent or FirmInternational ClassH01J 003/00AbstractA digital processing system including a central processing unit (CPU) and a digital signal processor (DSP) is optimized for digital signal processing applications, providing the central processing unit and digital signal processor with equal access to system resources such as system memory and connected I/O devices. The digital processing system includes two high-performance processor busses: one processor bus providing connection for one to four CPUs; the other processor bus providing connection for up to four DSPs. An advanced multi-ported memory controller interconnects the two processor busses with system memory and a system I/O bus, providing the CPUs and DSPs with equal and uniform access to all system memory and I/O resources. | |
