Patent ReferencesConvolutional encoder and sequential decoder with parallel architecture and block coding properties Method and apparatus for compressing and decompressing a digital video signal using predicted and error images Detection, correction and display of illegal color information in a digital video signal Digital VCR signal processing apparatus for concealing uncorrectable errors Error concealment control method and device of digital video signal Apparatus for concealing errors in a digital video processing system Encoding/decoding circuit, and digital video system comprising the circuit Compensation for truncation error in a digital video signal decoder Video signal decoding arrangement and method for improved error concealment Patent #: 5910827 InventorsApplicationNo. 922835 filed on 08/26/1997US Classes:375/240.12, Predictive375/240.27Error detection or correctionExaminersPrimary: Tung, BryanAttorney, Agent or FirmInternational ClassH04N 007/32AbstractAn MPEG digital video decoder system, method and computer program product are presented for monitoring decoding of an encoded digital video signal for one or more predefined illegal conditions. Error detection logic is coupled to the variable length (VLC) decoder, inverse quantizer (IQ), inverse discrete cosine transformer (IDCT) and motion compensator (MC) of the decoder for detecting an illegal condition within at least one of the VLC decoder, IQ, IDCT and MC during decoding of the encoded digital video signal. The monitored illegal conditions can include a VLC/IQ control error, an IQ level overrun, and IQ/IDCT buffer error, an MC idle error and an MC macroblock start error. Error signals are reported to a central error register which is monitored periodically by the decoder's control processor. The control processor initiates recovery within the decoder system prior to stoppage of the system due to the illegal condition. | |