Semiconductor integrated circuit manufacturing method and device
Patent 6051509 Issued on April 18, 2000. Estimated Expiration Date: 
March 25, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
March 25, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesAnti-oxidation layer formation by carbon incorporation Method and apparatus for depositing a multilayered low dielectric constant film Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor Process for producing a semiconductor device having a single thermal oxidizing step Patent #: 5915180 InventorApplicationNo. 047593 filed on 03/25/1998US Classes:438/758, COATING OF SUBSTRATE CONTAINING SEMICONDUCTOR REGION OR OF SEMICONDUCTOR SUBSTRATE257/E21.335, In Group IV semiconductor (EPO)257/E21.43, Recessing gate by adding semiconductor material at source (S) or drain (D) location, e.g., transist or with elevated single crystal S and D (EPO)257/E21.431, With source and drain recessed by etching or recessed and refi lled (EPO)257/E21.438, Using self-aligned silicidation, i.e., salicide (EPO)257/E21.444, Using dummy gate wherein at least part of final gate is self-aligned to dummy gate (EPO)257/E21.616, MIS technology (EPO)257/E29.021, For source or drain region of field-effect device (EPO)257/E29.13, Gate electrodes for nonplanar MOSFET (EPO)438/761, Multiple layers438/763Layers formed of diverse composition or by diverse coating processesExaminersPrimary: Niebling, John F.Assistant: Jones, Josetta Attorney, Agent or FirmInternational ClassesH01L 021/31H01L 021/469 Foreign Application Priority Data1997-03-25 JPAbstractA manufacturing method produces a semiconductor IC device which can maintain a low power consumption for electronic circuits and form gate-isolation layers of different thicknesses without increasing the manufacturing cost. The semiconductor IC device has gate-isolation layers of different thicknesses on the same semiconductor substrate surface. To form such gate-isolation layers, a silicon dioxide layer is formed in first and second regions. The dopant-concentration is adjusted in silicon dioxide layer that is to have a thickness different from the above silicon dioxide layer thickness in the second region B. A carbon-containing semiconductor layer is selectively formed in either the first region or the second region. Therefore, there is no need for additional steps for forming silicon dioxide layers of different thicknesses in the first region and in the second region. In addition, a carbon-containing semiconductor layer is selectively formed on desired areas of the semiconductor substrate where thinner oxide layer is to be formed. The semiconductor substrate is oxidized successively to have oxide layers of different thickness on the surface of the substrate in one step.Other References
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