Method for making asymmetrical N-channel and symmetrical P-channel devices
September 3, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesShort channel MOS devices and the method of manufacturing same Method for making a closed gate MOS transistor with self-aligned contacts with dual passivation layer Method of making a MOS transistor Method of manufacturing MIS semiconductor device Optimization of BV and RDS-on by graded doping in LDD and other high voltage ICs Field effect transistor structure and method Integrated circuit with planar dielectric layer Method for fabricating the LDD-MOSFET Method of making field effect transistor Field effect transistor with a lightly doped drain InventorsAssigneeApplicationNo. 711957 filed on 09/03/1996US Classes:438/286, Asymmetric438/231, Plural doping steps438/232, Plural doping steps438/305, Plural doping steps438/306, Plural doping steps438/307Using same conductivity-type dopantExaminersPrimary: Fahmy, WaelAssistant: Pham, Long Attorney, Agent or FirmForeign Patent References
International ClassesH01L 021/336FOR 168 AbstractAn asymmetrical N-channel IGFET and a symmetrical P-channel IGFET are disclosed. The N-channel IGFET includes heavily doped and ultra-heavily doped source regions, and lightly doped and heavily doped drain regions. The P-channel IGFET includes lightly doped and heavily doped source and drain regions. Forming the N-channel IGFET includes forming a gate with first and second opposing sidewalls, applying a first ion implantation to implant lightly doped N-type source and drain regions, applying a second ion implantation to convert the lightly doped N-type source region into a heavily doped N-type source region without doping the lightly doped N-type drain region, forming first and second spacers adjacent to the first and second sidewalls, respectively, and applying a third ion implantation to convert a portion of the heavily doped N-type source region outside the first spacer into an ultra-heavily doped N-type source region without doping a portion of the heavily doped N-type source region beneath the first spacer, and to convert a portion of the lightly doped N-type drain region outside the second spacer into a heavily doped N-type drain region without doping a portion of the lightly doped N-type drain region beneath the second spacer. Advantageously, both IGFETs reduce hot carrier effects, and the N-channel IGFET has particularly low source-drain series resistance.Other References
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