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Inventor
Assignee
Application No. 994518 filed on 12/19/1997
US Classes: 712/227 ,
Specialized instruction processing in support of testing, debugging, emulation 714/34 ,
Halt, clock, or interrupt signal (e.g., freezing, hardware breakpoint, single-stepping) 714/38 ,
Of computer software 717/128 Tracing
Examiners Primary:
Pan, Daniel H.
Attorney, Agent or Firm
Foreign Patent References 316609 EP. 05/13/1989 0530816A3 EP. 03/13/1993 636976 EP. 02/13/1995 762276 EP. 03/13/1997 849670 EP. 06/13/1998 59-194245 JP. 11/13/1984
International Classes G06F 011/34
G06F 011/28
Abstract A processor has both a serial debug port and a parallel debug port. The processor includes a processor core. The serial debug port is formed of a plurality of pins configured to send and receive signals to and from external software debug equipment. The parallel debug port is formed of a plurality of pins and configured to send and receive signals from external software debug equipment. A plurality of debug registers are accessible to the serial debug port and the parallel debug port. The debug registers are also coupled to the processor core for receiving and providing debug data and control signals. The processor core performs various software debug operations in response to signals from the external software debug equipment sent over one of the parallel and serial debug ports and communicates the results of the debug operation back over one of the serial and parallel debug ports.
Other References IBM Technical Disclosure Bulletin, "Trace Array", vol. 35, No. 2, Jul. 1992, pp. 138-140 IBM Technical Disclosure Bulletin "Tailorable Embedded Event Trace", vol. 34, No. 7B, Dec. 1991, pp. 259-261 Intel "Pentium™ Processor User's Manual vol. 3: Architecture and Programming Manual", 1994, pp. 17-1 thru 17-9 K5 HDT, e-mail describing K5 HDT, Jan. 11, 1997, pp. 1-6 Motorola "CPU32 Reference Manual", pp 7-1 thru 7-13 (admitted prior to Apr. 8, 1997) Motorola "MEVB Quick Start Guide", pp. 3-5 thru 7-2 (admitted prior to Apr. 8, 1997) Revill, Geoff, "Advanced On-chip Debug for ColdFire Developers", Embedded System Engineering, Apr./May 1997, pp. S2-S4 Larus, James R., Efficient Program Tracing, 8153 Computer, No. 5, May 26, 1993, Los Alamitos, CA, pp. 52-61 Advanced Micro Devices, "Am29040™ Microprocessor User's Manual--29K Family", Advanced Micro Devices, Inc. 1994, pp. 12-1 through 12-26 O'Farrell, Ray, "Choosing a Cross-Debugging Methodology", Embedded Systems Programming, Aug. 1997, pp. 84-89 Ganssle, Jack G., "Vanishing Visibility, Part 2", Embedded Systems Programming, Aug. 1997, pp. 113-115 Ojennes, Dan, "Debugging With Real-Time Trace", Embedded Systems Programming, Aug. 1997, pp. 50-52, 54, 56, and 5
Field of Search Scan path testing (e.g., level sensitive scan design (LSSD)) Built-in hardware for diagnosing or testing within-system component (e.g., microprocessor test mode circuit, scan path) Performance monitoring for fault avoidance Halt, clock, or interrupt signal (e.g., freezing, hardware breakpoint, single-stepping) Fault locating (i.e., diagnosis or testing) Component dependent technique Clock or synchronization Of computer software Device response compared to expected fault-free response Built-in testing circuit (BILBO) Substituted or added instruction (e.g., code instrumenting, breakpoint instruction) Including delay line or charge transfer device Opposite polarity Plural clock outputs with multiple inputs Digital Signal processor Specialized instruction processing in support of testing, debugging, emulation
December 19, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
