Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion
September 20, 2019. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod for fabricating semiconductor device with interconnections buried in trenches Dual damascene with a protective mask for via etching Diffusion barrier for electrical interconnects in an integrated circuit Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC) Method of manufacturing copper interconnect with top barrier layer Method for forming multileves interconnections for semiconductor fabrication Process for forming a semiconductor device Protected encapsulation of catalytic layer for electroless copper interconnect Method for producing ultra-fine interconnection features InventorsAssigneeApplicationNo. 398292 filed on 09/20/1999US Classes:438/687, Copper of copper alloy conductor257/E21.579, For "dual damascene" type structures (EPO)257/E21.584, Barrier, adhesion or liner layer (EPO)438/624, Separating insulating layer is laminate or composite of plural insulating materials438/637, With formation of opening (i.e., viahole) in insulative layer438/639, Having viahole with sidewall component438/666, Specified configuration of electrode or contact438/672Plug formation (i.e., in viahole)ExaminersPrimary: Niebling, John F.Assistant: Gurley, Lynne A. Attorney, Agent or FirmInternational ClassH01L 021/44AbstractA method of fabricating damascene vias has been achieved. Diffusion of copper into dielectric layers due to overetch of the passivation layer is eliminated by a barrier layer. The method can be used to form dual damascene interconnects. Copper traces through an isolation layer are provided overlying a semiconductor substrate. A passivation layer is deposited overlying the copper traces and the isolation layer. A dielectric layer is deposited. A cap layer is deposited. The cap layer and the dielectric layer are patterned to expose the top surface of the passivation layer and to form trenches for the damascene vias. A barrier layer is deposited overlying the passivation layer, the dielectric layer, and the cap layer. The barrier layer is etched though to expose the top surfaces of the cap layer and the passivation layer. The barrier layer isolates the sidewalls of the trenches. The passivation layer is etched through to complete damascene vias. The barrier layer prevents copper sputtering onto the dielectric layer during the step of etching through the passivation layer.Field of SearchCopper of copper alloy conductorMultiple metal levels, separated by insulating layer (i.e., multiple level metallization) At least one layer forms a diffusion barrier Diverse conductive layers limited to viahole/plug Simultaneous (e.g., chemical-mechanical polishing, etc.) Separating insulating layer is laminate or composite of plural insulating materials Having planarization step Simultaneously by chemical and mechanical means With formation of opening (i.e., viahole) in insulative layer Having viahole with sidewall component Plug formation (i.e., in viahole) Specified configuration of electrode or contact | |
