2F-square memory cell for gigabit memory applications
January 26, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSemiconductor memory cell Non-volatile semiconductor memory device Erasable electrically programmable read only memory cell using trench edge tunnelling Non-volatile semiconductor memory device and method of the manufacture thereof Three-dimensional memory cell with integral select transistor Floating gate memory cell and device Dram cell formed on an insulating layer having a buried semiconductor pillar structure and a manufacturing method thereof Dram with a vertical capacitor and transistor 5016067 5016068 InventorsApplicationNo. 013509 filed on 01/26/1998US Classes:438/238, Including passive device (e.g., resistor, capacitor, etc.)257/E21.693, For vertical channel (EPO)257/E27.086, Storage electrode stacked over the transistor257/E27.091, Transistor in trench (EPO)257/E27.096, Vertical transistor (EPO)257/E27.103, Electrically programmable ROM (EPO)438/242, Including transistor formed on trench sidewalls438/245, With epitaxial layer formed over the trench438/263, Tunneling insulator438/266, Having additional, nonmemory control electrode or channel portion (e.g., for accessing field effect transistor structure, etc.)438/270Gate electrode in trench or recess in semiconductor substrateExaminersPrimary: Fahmy, WaelAssistant: Coleman, William David Attorney, Agent or FirmInternational ClassesH01L 021/824.9H01L 029/788 AbstractA densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the bitlines. The array also has vertical pillars, each having a channel formed between source and drain regions. Two transistors are formed per pillar. This is achieved by forming two gates per pillar formed on opposite pillar sidewalls which are along the bitline direction. This forms two wordlines or gates per pillar arranged in the wordline direction. The source regions are self-aligned and located below the pillars. The source regions of adjacent bit lines are isolated from each other without increasing the cell size.Other References
Field of SearchHaving additional gate electrode surrounded by dielectric (i.e., floating gate)Including forming gate electrode in trench or recess in substrate Gate electrode in trench or recess in semiconductor substrate Including passive device (e.g., resistor, capacitor, etc.) Including transistor formed on trench sidewalls With epitaxial layer formed over the trench Tunneling insulator Having additional, nonmemory control electrode or channel portion (e.g., for accessing field effect transistor structure, etc.) With floating gate electrode | |
