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AbstractA low power serial A/D converter cascades multiple stages (20) of a novel track-and-hold circuit (22) to implement a pipelined A/D converter. The track-and-hold circuit (22) is implemented using a differential structure to cancel out signal droop. This allows extremely high tracking bandwidths to be achieved while maintaining long hold times. Each stage (20) of the pipeline includes a binary quantizing circuit (24) which performs a 1-bit binary estimate of the data and a summing circuit (26) which updates the output of its track-and-hold circuit (22) to allow the next bits to be decided by the following stages. | InventorAssigneeApplicationNo. 027759 filed on 02/23/1998US Classes:341/161, Acting sequentially327/491, With emitter follower341/155Analog to digital conversionField of Search341/161, Acting sequentially341/135, Current mirror341/136, Field effect transistor341/143, Differential encoder and/or decoder (e.g., delta modulation, differential pulse code modulation)341/124, Sampled and held input signal with linear return to datum341/125, Sampled and held input signal with nonlinear return to datum327/65, Differential input327/407, Converging with plural inputs and single output327/411, Bipolar transistor327/491With emitter followerExaminersPrimary: Williams, Howard L.Assistant: JeanPierre, Peguy Attorney, Agent or FirmUS Patent References4369500, High speed NXM bit digital, repeated addition type multiplying circuitIssued on: 01/18/1983 Inventor: Fette4665382, Analog-to-digital conversion Issued on: 05/12/1987 Inventor: Morgan4740907, Full adder circuit using differential transistor pairs Issued on: 04/26/1988 Inventor: Shimizu , et al.4916653, Adder using multi-state logic Issued on: 04/10/1990 Inventor: Shimizu, et al.4918640, Adder cell having a sum part and a carry part Issued on: 04/17/1990 Inventor: Heimsch, et al.5047772, Digital error correction system for subranging analog-to-digital converters Issued on: 09/10/1991 Inventor: Ribner5059829, Logic level shifting circuit with minimal delay Issued on: 10/22/1991 Inventor: Flannagan, et al.5130572, Operational track-and-hold amplifier Issued on: 07/14/1992 Inventor: Stitt, et al.5132921, High speed digital computing system Issued on: 07/21/1992 Inventor: Kelley, et al.5134579, Digital adder circuit Issued on: 07/28/1992 Inventor: Oki, et al.5237332, Receiver distortion correction circuit and method Issued on: 08/17/1993 Inventor: Estrick, et al.5315170, Track and hold circuit Issued on: 05/24/1994 Inventor: Vinn, et al.5347482, Multiplier tree using nine-to-three adders Issued on: 09/13/1994 Inventor: Williams5444447, Analog-digital converter with distributed sample-and-hold circuit Issued on: 08/22/1995 Inventor: Wingender5471413, Fast adder chain Issued on: 11/28/1995 Inventor: Sali, et al.5485106, ECL to CMOS converter Issued on: 01/16/1996 Inventor: Drost, et al.5491653, Differential carry-save adder and multiplier Issued on: 02/13/1996 Inventor: Taborn, et al.5499027, Digitally self-calibrating pipeline analog-to-digital converter Issued on: 03/12/1996 Inventor: Karanicolas, et al.5510736, Differential sampler circuit Issued on: 04/23/1996 Inventor: Van de Plassche5586071, Enhanced fast multiplier Issued on: 12/17/1996 Inventor: Flora5596520, CMOS full adder circuit with pair of carry signal lines Issued on: 01/21/1997 Inventor: Hara, et al.5635937, Pipelined multi-stage analog-to-digital converter Issued on: 06/03/1997 Inventor: Lim, et al.5638071Efficient architecture for correcting component mismatches and circuit nonlinearities in A/D converters Issued on: 06/10/1997 Inventor: Capofreddi, et al. International ClassH03M 001/38 |