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US Patent 6037891 - Low power serial analog-to-digital converter

US Patent Issued on March 14, 2000
Estimated Patent Expiration Date: Icon_subject February 23, 2018Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
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Abstract

A low power serial A/D converter cascades multiple stages (20) of a novel track-and-hold circuit (22) to implement a pipelined A/D converter. The track-and-hold circuit (22) is implemented using a differential structure to cancel out signal droop. This allows extremely high tracking bandwidths to be achieved while maintaining long hold times. Each stage (20) of the pipeline includes a binary quantizing circuit (24) which performs a 1-bit binary estimate of the data and a summing circuit (26) which updates the output of its track-and-hold circuit (22) to allow the next bits to be decided by the following stages.

Inventor

Assignee

Application

No. 027759 filed on 02/23/1998

US Classes:

341/161, Acting sequentially327/491, With emitter follower341/155Analog to digital conversion

Field of Search

341/161, Acting sequentially341/135, Current mirror341/136, Field effect transistor341/143, Differential encoder and/or decoder (e.g., delta modulation, differential pulse code modulation)341/124, Sampled and held input signal with linear return to datum341/125, Sampled and held input signal with nonlinear return to datum327/65, Differential input327/407, Converging with plural inputs and single output327/411, Bipolar transistor327/491With emitter follower

Examiners

Primary: Williams, Howard L.
Assistant: JeanPierre, Peguy

Attorney, Agent or Firm

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International Class

H03M 001/38

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