Scheduling instructions with different latencies
Patent 6035389 Issued on March 7, 2000. Estimated Expiration Date: 
August 11, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
August 11, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMulti-threaded microprocessor architecture utilizing static interleaving System and method for ring latency measurement and correction Scan chain for rapidly identifying first or second objects of selected types in a sequential list Processor having execution core sections operating at different clock rates Patent #: 5828868 InventorsApplicationNo. 132043 filed on 08/11/1998US Classes:712/216, DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTION712/215, Simultaneous issuance of multiple instructions712/217Scoreboarding, reservation station, or aliasingExaminersPrimary: Treat, William M.Attorney, Agent or FirmInternational ClassG06F 009/38AbstractAn apparatus includes a clock to produce pulses and an electronic hardware structure having a plurality of rows and one or more ports. Each row is adapted to record a separate latency vector written through one of the ports. The latency vector recorded therein is responsive to the clock. A method of dispatching instructions in a processor includes updating a plurality of expected latencies to a portion of rows of a register latency table, and decreasing the expected latencies remaining in other of the rows in response to a clock pulse. The rows of the portion correspond to particular registers. | |
