Pipeline analog-to-digital conversion that reduces the accumulation offset errors
Patent 6028546 Issued on February 22, 2000. Estimated Expiration Date: 
December 15, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 15, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3035258 3187325 Serial-type A/D converter utilizing folding circuit cells Analog-digital converter Pipelined A/D converter Folding circuit and serial-type A/D converter High-speed A/D conversion using a series of one-bit conversion stages Analog to digital converter using complementary differential emitter pairs Patent #: 5550492 InventorsAssigneeApplicationNo. 990334 filed on 12/15/1997US Classes:341/161, Acting sequentially341/155Analog to digital conversionExaminersPrimary: Williams, Howard L.Assistant: JeanPierre, Peguy Attorney, Agent or FirmInternational ClassH03M 001/38Foreign Application Priority Data1996-12-16 SEAbstractPipeline A/D-conversion of an analog input signal is performed according to a new and inventive algorithm which generates a Gray coded digital output signal. A pipeline A/D-converter comprises a number of cascaded stages through which the analog input signal is propagated. Each stage generally generates an output bit of the digital output signal, and furthermore processes the pipeline signal. According to the inventive Gray coding algorithm, the output bit generated in a stage determines whether or not the pipeline signal of that stage is inverted. In a pipeline A/D-converter based on the Gray coding algorithm according to the invention, the accumulation of offset errors will generally be very low. Furthermore, the fact that the signal inversion is digitally controlled enables high precision implementations which further improve the performance of the inventive pipeline A/D-converter. In another embodiment of the invention, the Gray coding algorithm is modified to form a second algorithm which makes low device count implementations possible.Other References
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