CMOS semiconductor devices and method of formation

Patent 6027961 Issued on February 22, 2000. Estimated Expiration Date:

June 30, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Titanium nitride MOS device gate electrode and method of producing
Patent #: 4605947
Issued on: 08/12/1986
Inventor: Price , et al.

CMOS device and process
Patent #: 5268590
Issued on: 12/07/1993
Inventor: Pfiester, et al.

Video compression/expansion apparatus for digital VCR
Patent #: 5457580
Issued on: 10/10/1995
Inventor: Yoo

Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer
Patent #: 5600169
Issued on: 02/04/1997
Inventor: Burgener, et al.

Method of controlling dopant diffusion and metal contamination in thin polycide gate conductor of mosfet device Patent #: 5923999
Issued on: 07/13/1999
Inventor: Balasubramanyam, et al.

Inventors

Assignee

Motorola, Inc.

Application

No. 107963 filed on 06/30/1998

US Classes:

438/199, Complementary insulated gate field effect transistors (i.e., CMOS)257/E21.632, Complementary field-effect transistors, e.g., CMOS (EPO)257/E27.064, Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS (EPO)438/584, COATING WITH ELECTRICALLY OR THERMALLY CONDUCTIVE MATERIAL438/592Possessing plural conductive layers (e.g., polycide)

Examiners

Primary: Niebling, John F.
Assistant: Lattin, Christopher

International Class

H01L 021/823.8

Abstract

In one embodiment, a metal layer (18) is formed over a gate dielectric layer (14, 16) on a semiconductor substrate. A masking layer (20) is patterned to mask a portion of the metal layer (18). An exposed portion of the metal layer (18) is nitrided to form a conductive nitride layer (24). The masking layer (20) is removed and the conductive nitride layer (24) is patterned to form a first gate electrode (23) having a first work function value, and the conductive layer (18) is patterned to form a second gate electrode (25) having a second work function value which is different from that of the first work function value.