Split embedded DRAM processor
December 23, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod and apparatus for transferring vector data between parallel processing system with registers & logic for inter-processor data communication independents of processing operations Multi-mode DRAM controller System with a multiport memory and N processing units for concurrently/individually executing 2N-multi-instruction-words at first/second transitions of a single clock cycle Microcomputer including memory controller for DRAM Reconfigurable memory processor Co-processor monitoring address generated by host processor to obtain DMA parameters in the unused portion of instructions Apparatus for executing respective portions of a process by main and sub CPUS Single chip dual processor High speed programmable logic controller Method and apparatus for the transparent emulation of an existing instruction-set architecture by an arbitrary underlying instruction-set architecture InventorApplicationNo. 997364 filed on 12/23/1997US Classes:712/24, Long instruction word712/34, Including coprocessor712/215Simultaneous issuance of multiple instructionsExaminersPrimary: Donaghue, Larry D.Attorney, Agent or FirmInternational ClassG06H 015/00AbstractA processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural components jointly implement a single processor and instruction set. Advantageously, the embedded logic on the DRAM chip implements the memory intensive processing tasks, thus reducing the amount of traffic that needs to be bussed back and forth between the CPU core and the embedded DRAM chips. The embedded DRAM logic monitors and manipulates the instruction stream into the CPU core. The architecture of the instruction set, data paths, addressing, control, caching, and interfaces are developed to allow the system to operate using a standard programming model. Specialized video and graphics processing systems are developed. Also, an extended very long instruction word (VLIW) architecture implemented as a primary VLIW processor coupled to an embedded DRAM VLIW extension processor efficiently deals with memory intensive tasks. In different embodiments, standard software can be accelerated either with or without the express knowledge of the processor. | |
