Patent ReferencesFloating gate memory device with facing asperities on floating and control gates Memory cell for a dense EPROM Method of fabricating a textured tunnel oxide for EEPROM applications Patent #: 5429966 InventorsApplicationNo. 087473 filed on 05/29/1998US Classes:257/321, With thin insulator region for charging or discharging floating electrode by quantum mechanical tunneling257/316, With additional contacted control electrode257/319, Plural additional contacted control electrodes257/E21.209, Making electrode structure comprising conductor-insulator-conuctor-insulator-semiconductor, e.g., gate stack for non-volatile memory (EPO)257/E29.162, Insulating materials for IGFET (EPO)257/E29.304Charging by tunneling of carriers (e.g., Fowler-Nordheim tunneling) (EPO)ExaminersPrimary: Saadat, MahshidAssistant: Eckert, II, George C. Attorney, Agent or FirmInternational ClassH01L 029/788AbstractA method and structure for textured surfaces in non volatile floating gate tunneling oxide (FLOTOX) devices, e.g. FLOTOX transistors, are provided. The present invention capitalizes on using "self-structured masks" and a controlled etch to form nanometer scale microtip arrays to form the textured surfaces. The present invention further employs atomic layer epitaxy (ALE) to create a very conformal tunnel oxide layer which complements the nanometer scale microtip arrays. The resulting structure provides a higher tunneling current than currently exists in FLOTOX technology. The improved tunneling currents at low voltages can make these FLOTOX devices suitable for replacing DRAMS.Other References
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