Patent ReferencesInteractive display apparatus and method with viewer position compensation Address translator for a shared memory computing system Tiled memory addressing with programmable tile dimensions Method and apparatus for dynamic memory management by association of free memory blocks using a binary tree organized in an address and size dependent manner Patent #: 5930827 InventorsAssigneeApplicationNo. 033371 filed on 03/02/1998US Classes:345/543, Memory allocation345/502, Plural graphics processors345/531, Graphic display memory controller345/566, Address manipulation711/153, Shared memory partitioning711/170, Memory configuring711/173Memory partitioningExaminersPrimary: Tung, Kee M.Attorney, Agent or FirmInternational ClassG06F 015/167AbstractA method and apparatus for memory allocation in a multi-processor system is accomplished by mapping portions of a shared memory to a first and second processor. The mapping is performed such that either of the processors' portions can be enlarged or reduced based on the memory that is located between the portions allocated to the processors. When a processor requests additional memory and there is sufficient free memory between the processors' respective portions, the appropriate amount of the free memory is allocated to the requesting processor. | |