Error correcting code retrofit method and apparatus for multiple memory configurations
December 3, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of detecting and correcting errors in digital data storage systems Method and device for generating check bits protecting a data word Dram on-chip error correction/detection Computer system operation with corrected read data function Fault-tolerant memory system with graceful degradation Data formater/converter for use with solid-state disk memory using storage devices with defects Error detection and correction apparatus in a BY-4 RAM Device Method and structure for providing error correction code and parity for each byte on SIMM's Method and structure for providing error correction code for each byte on SIMM'S Method of using stream buffer to perform operation under normal operation mode and selectively switching to test mode to check data integrity during system operation InventorsApplicationNo. 984240 filed on 12/03/1997US Classes:714/762, Burst error correction714/718, Memory testing714/763, Memory access714/805Storage accessing (e.g., address parity check)ExaminersPrimary: Moise, Emmanuel L.Attorney, Agent or FirmInternational ClassesH03M 013/00G11C 029/00 AbstractA method and apparatus are described for providing error correcting code (ECC) which may be incorporated into a computer system which includes one of a plurality of memory configurations and which may include a pre-existing error control feature. A data store operation causes the receipt of a word including data bits and check bits generated by a pre-existing error control feature. The data and check bits of the received word are used to generate additional check bits based upon the configuration of the computer system memory. The additionally generated check bits are stored in the memory along with the received word. Upon a subsequent data fetch operation which retrieves the word and check bits the check bits are decoded thereby providing error detection and correction in the retrieved word for single and multiple bit errors including the failure of an entire memory chip. The invention provides 84/72 ECC for computer systems having a four bit per chip memory configuration and 88/72 ECC for computer systems having an eight bit per chip memory configuration. Further embodiments describe the detection and communication of uncorrectable errors.Field of SearchMemory testingDouble error correcting with single error correcting code Parallel generation of check bits Error correcting code with additional error detection code (e.g., cyclic redundancy character, parity) Random and burst error correction Burst error correction Memory access Error correct and restore Error pointer Check bits stored in separate area of memory Code word for plural n-bit (n>1) storage units (e.g., x4 DRAM's) Error correction code for memory address Dynamic data storage Disk array Solid state memory Hamming code Syndrome computed Parity bit Parity generator or checker circuit detail Even and odd parity Parity prediction Plural dimension parity check Storage accessing (e.g., address parity check) | |
