Apparatus and method of maintaining cache coherency in a multi-processor computer system with global and local recently read states
February 17, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMultiprocessor system with cache memory Computer hierarchy control Multiple caches using state information indicating if cache line was previously modified and type of access rights granted to assign access rights to cache line Coherent copyback protocol for multi-level cache memory systems Adaptive scalable cache coherence network for a multiprocessor data processing system Snooper circuit of a multi-processor system Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories Cache coherency where multiple processors may access the same data over independent access paths Patent #: 5845327 InventorsApplicationNo. 024307 filed on 02/17/1998US Classes:711/141, Coherency711/3, Addressing cache memories711/118, Caching711/123, User data cache and instruction data cache711/144, Cache status data bit711/146, Snooping711/154, Control technique711/155, Read-modify-write (RMW)711/210Resolving conflict, coherency, or synonym problemExaminersPrimary: Thai, Tuan V.Attorney, Agent or FirmInternational ClassesG06F 012/00G06F 013/00 AbstractA multi-processor computer system with clustered processing units uses a cache coherency protocol having a "recent" coherency state to indicate that a particular cache block containing a valid copy of a value (instruction or data) was the most recently accessed block out of a group of cache blocks in different caches (but at the same cache level) that share valid copies of the value. The "recent" state can advantageously be used to implement optimized memory operations such as intervention, by sourcing the value from the cache block in the "recent" state, as opposed to sourcing the value from system memory (RAM), which would be a slower operation. In an exemplary implementation, the hierarchy has two cache levels supporting a given processing unit cluster; the "recent" state can be applied to a plurality of caches at the first level (each associated with a different processing unit cluster), and the "recent" state can further be applied to one of the caches at the second level. | |
