Method and apparatus for eliminating bitline voltage offsets in memory devices
January 29, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProgrammable read only memory for electronic engine control Semiconductor memory apparatus with internal synchronization Semiconductor memory having an operation margin against a write recovery time High speed semiconductor memory having a direct-bypass signal path Semiconductor integrated circuit Semiconductor memory device Anti-noise and auto-stand-by memory architecture VLSI memory with an improved sense amplifier with dummy bit lines for modeling addressable bit lines Memory device with current path cut-off circuit for sense amplifier Method of operating the semiconductor memory storing analog data and analog data storing apparatus InventorsAssigneeApplicationNo. 015427 filed on 01/29/1998US Classes:716/17, Programmable integrated circuit (e.g., basic cell, standard cell, macrocell)257/E27.099, Load element being a MOSFET transistor (EPO)700/34, Variable716/8FloorplanningExaminersPrimary: Teska, Kevin J.Assistant: Sergent, Douglas W. Attorney, Agent or FirmInternational ClassG11C 011/407AbstractDisclosed is a method of designing a memory device that has substantially reduced bitline voltage offsets. The method includes providing a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline. The method also includes designing a six transistor core cell having a bitline and a complementary bitline, and designing a flipped six transistor core cell that has a flipped bitline and a flipped complementary bitline. Further, the method includes arranging a six transistor core cell followed by a flipped six transistor core cell along each of the multiple pairs of the global bitline and the global complementary bitline. Preferably, the bitline of the six transistor core cell is coupled with the flipped complementary bitline of the flipped six transistor core cell, and the complementary bitline of the six transistor core cell is coupled to the flipped bitline of the flipped six transistor core cell.Other References
| |
