High speed buffer management of share memory using linked lists and plural buffer managers for processing multiple requests concurrently
Method and apparatus for placing multiple frames of data in a buffer in a direct memory access transfer Patent #: 5828901
ApplicationNo. 926374 filed on 09/09/1997
US Classes:710/56, Buffer space allocation or deallocation710/22Direct Memory Accessing (DMA)
ExaminersPrimary: Follansbee, John
Attorney, Agent or Firm
International ClassG06F 012/00
AbstractAn image acquisition apparatus, for acquiring frames of a video signal and storing these frames in a computer memory, is disclosed. An analog video input signal, comprising a sequence of video frames, is digitized by an A/D converter. The resulting digitized frames are selectively gated into a frame acquisition buffer. The frame acquisition buffer includes two or more memory segments, each configured to store a digitized video frame. A DMA controller transfers video frames from the frame acquisition buffer to the computer memory via a peripheral bus. Frame acquisition control logic (e.g. a second DMA controller) selects which video frames of the frame sequence are to be acquired into the frame acquisition buffer. The frame acquisition control logic and the DMA controller are coordinated by a status memory which contains a status flag for each memory segment. The frame acquisition control logic: checks a status flag to ensure that the corresponding memory segment is available before commanding the memory segment to be overvritten with a new video frame; and changes the status flag to indicate unavailability. The DMA controller updates a status flag to indicate availability when it finishes transferring the data contents of the corresponding memory segment. The frame acquisition control logic and the DMA controller operate concurrently.