U.S. patents available from 1976 to present.
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Location dependent maximum transition run length code with alternating code word length and efficient K constraint

Patent 6011497 Issued on January 4, 2000. Estimated Expiration Date: Icon_subject March 31, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Viterbi equalizer and recording/reproducing device using the same
Patent #: 5341386
Issued on: 08/23/1994
Inventor: Shimoda, et al.

Data recording method and data recording apparatus using a digital sum value of a coded signal
Patent #: 5451943
Issued on: 09/19/1995
Inventor: Satomura

Maximum likelihood sequence detector
Patent #: 5502735
Issued on: 03/26/1996
Inventor: Cooper

Position detecting device using run position and run length of normalized projection data
Patent #: 5553169
Issued on: 09/03/1996
Inventor: Mizuoka

Method and apparatus for detecting and decoding data in a PRML class-IV digital communication channel
Patent #: 5576707
Issued on: 11/19/1996
Inventor: Zook

Method and apparatus for implementing codes with maximum transition run length
Patent #: 5731768
Issued on: 03/24/1998
Inventor: Tsang

Method and apparatus for implementing maximum transition run codes Patent #: 5859601
Issued on: 01/12/1999
Inventor: Moon, et al.

Inventors

Application

No. 052582 filed on 03/31/1998

US Classes:

341/59, To or from run length limited codes341/50DIGITAL CODE TO DIGITAL CODE CONVERTERS

Examiners

Primary: Young, Brian

Attorney, Agent or Firm

International Class

H03M 007/46

Abstract

An encoder and a method of encoding successive data words into successive code words having alternating code word lengths. Each code word has a plurality of bit locations. A first maximum transition run constraint is imposed on a first set of the bit locations, wherein each bit location in the first set is spaced S bit locations apart from one another, and S is an integer greater than one. A second maximum transition run constraint, which is different than the first maximum transition run constrain, is imposed on a second set of the bit locations, wherein the second set comprises each of the bit locations that are not in the first set. The alternating code word lengths and the value of S are defined such that corresponding bit locations in successive code words have the same maximum transition run constraint.

Other References

  • B. Brickner and J. Moon, "A High-Dimensional Signal Space Implementation of FDTS/DF", IEEE Transactions on Magnetics, Sep. 1996, pp. 3941-3943
  • B. Brickner and J. Moon, "Maximum Transition Run Codes for Data Storage Systems", IEEE Transaction on Magnetics, Sep. 1996, pp. 3992-399
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