Patent ReferencesMethod of making an intergrated vertical NPN and vertical oxide fuse programmable memory cell Electric fuse for a redundancy circuit Module level electronic redundancy ZAG fuse for reduced blow-current application Vertical fuse device Fuse bank Laser fusible link structure for semiconductor devices Space saving laser programmable fuse layout Patent #: 5844296 InventorsAssigneeApplicationNo. 140573 filed on 08/26/1998US Classes:257/529, Including programmable passive component (e.g., fuse)257/209, Programmable signal paths (e.g., with fuse elements, laser programmable, etc)257/E23.149Comprising fuses, i.e., connections having their state changed from conductive to nonconductive (EPO)ExaminersPrimary: Saadat, MahshidAssistant: Eckert, George Attorney, Agent or FirmForeign Patent References
International ClassH01L 029/00AbstractA semiconductor device includes an array of electrical fuses having a structure which permits tight fuse pitches while enabling electrical fusing at voltages of about 10 volts or less. The fuses are useful to replace defective components of the device and/or to permit custom wiring. The semiconductor device includes a substrate with a tight pitch array of fuses including a plurality of fuse links of selective cross sectional area in closely adjacent arrangement, each connected at one end to an individual connector terminal of larger cross sectional area than that of the fuse link, and at another end to a common connector terminal of larger cross sectional area than that of the individual connector terminals. The common connector terminal is typically held at a less positive potential than one of the individual connector terminals during the time a fuse link thereat is to be opened such that electron flow is in a direction from the common connector terminal to the fuse link. The common connector terminal cross sectional area is desirably about 2 or more times that of the individual fuse links to enable electrical fusing at voltages of about 10 volts or less. | |