Multiple-bit random-access memory array
Patent 6005793 Issued on December 21, 1999. Estimated Expiration Date: 
March 31, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
March 31, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesBit-line isolated, CMOS sense amplifier High performance RAM array circuit employing self-time clock generator for enabling array accessess Patent #: 5619464 InventorApplicationNo. 052518 filed on 03/31/1998US Classes:365/154, Flip-flop (electrical)365/185.01FLOATING GATEExaminersPrimary: Nelms, David C.Assistant: Phung, Anh International ClassesG11C 011/00G11C 016/04 AbstractA cache memory consists of plurality of memory bits within a random-access memory (RAM) cell. An extra address decode circuit is needed to select a single memory bit within the multi-bit RAM cell before normal access of RAM array circuit. Combining of multiple bits into a RAM cell reduces the number of interconnections in comparison to single bit RAM cell. This technique eliminates the need to break up the cache array into multiple sets for reducing power dissipation. The area advantages are also from optimal layout of multi-bit RAM cell, address decoder, and sense amplifier unit. Furthermore, the interconnections can be widened to reduce the RC delay as it is a dominating factor in future technology advancement. The multiplexing of the bits are done before the row decoding thus reducing one level of multiplexing after reading of data from the sense amplifier units.Other References
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