Multiple graphics pipeline integration with a windowing system through the use of a high speed interconnect to the frame buffer

Patent 5995121 Issued on November 30, 1999. Estimated Expiration Date:

October 16, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Single chip frame buffer and graphics accelerator
Patent #: 5694143
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Inventors

Application

No. 951356 filed on 10/16/1997

US Classes:

345/520, Interface (e.g., controller)345/502Plural graphics processors

Examiners

Primary: Tung, Kee M.
Assistant: Luu, Sy D.

International Classes

G06F 015/16
G06F 013/14

Abstract

An improved method of incorporating a high performance graphics device into a base graphics subsystem of a processor includes two pairs of interface chips. One pair of interface chips is used to transfer pixel data between a base graphics system and the high performance graphics device, while the second pair of interface chips is used to transfer commands between the graphics device and the base graphics system. One of the pair of interface chips that is used to transfer pixel data is coupled to a bus within the base graphics subsystem while the second one of the pair is coupled to the graphics device. With such an arrangement, a high speed interface allows for pixel data to be fed directly to the frame buffer of the graphics subsystem, enabling the windows that are rendered by two different graphics systems to share a frame buffer memory.