Method for cleaning semiconductor wafers
August 13, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesApparatus for in-situ chamber cleaning Low-temperature in-situ dry cleaning process for semiconductor wafers Remote plasma enhanced CVD method and apparatus for growing an epitaxial semiconductor layer Method for enhancing nitridation and oxidation growth by introducing pulsed NF3 Method of forming silicon carbide Method for improving stability of tungsten chemical vapor deposition Low-temperature in-situ dry cleaning process for semiconductor wafer Method for plasma etching or cleaning with diluted NF3 Apparatus for selective chemical vapor deposition of dielectric, semiconductor and conductive films on semiconductor and metallic substrates Method of chamber cleaning in MOCVD application Patent #: 5658391 InventorApplicationNo. 915517 filed on 08/13/1997US Classes:438/758, COATING OF SUBSTRATE CONTAINING SEMICONDUCTOR REGION OR OF SEMICONDUCTOR SUBSTRATE438/905, CLEANING OF REACTION CHAMBER438/906CLEANING OF WAFER AS INTERIM STEPExaminersPrimary: Chaudhari, ChandraAssistant: Berry, Renee R. Attorney, Agent or FirmInternational ClassH01L 021/31AbstractA low temperature in-situ precleaning process for a semiconductor surface is disclosed. Ambient reactant gases, such as NF3 and GeH4, having a partial pressure of between approximately 10-8 and 700 Torr, are pulsed in a batch furnace at temperatures in the approximate range of 250 to 950 degrees Celsius and pressure in the approximate range of 4×103 to 20×103 Torr. This forms material on the surface that easily vaporizes in that temperature and pressure range, providing a clean surface for formation of the next layer. A similar in-situ cleaning process is performed at temperature ranges of between approximately 300 to 1,000 degrees Celsius for the equipment utilized in processing semiconductor substrates.Field of SearchSelective deposition of conductive layerForming tapered profile (e.g., tapered etching, etc.) Including change in etch influencing parameter (e.g., energizing power, etchant composition, temperature, etc.) Silicon oxide or glass Silicon nitride COATING OF SUBSTRATE CONTAINING SEMICONDUCTOR REGION OR OF SEMICONDUCTOR SUBSTRATE CLEANING OF REACTION CHAMBER CLEANING OF WAFER AS INTERIM STEP | |
