2F-square memory cell for gigabit memory applications
January 22, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSemiconductor memory cell Non-volatile semiconductor memory device Erasable electrically programmable read only memory cell using trench edge tunnelling Tunnel injection controlling type semiconductor device controlled by static induction effect Non-volatile semiconductor memory device and method of the manufacture thereof Three-dimensional memory cell with integral select transistor Floating gate memory cell and device Dram cell formed on an insulating layer having a buried semiconductor pillar structure and a manufacturing method thereof Dram with a vertical capacitor and transistor 5016067 InventorsApplicationNo. 787418 filed on 01/22/1997US Classes:257/296, Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell)257/316, With additional contacted control electrode257/330, Gate electrode in groove257/623, Mesa structure (e.g., including undercut or stepped mesa configuration or having constant slope taper)257/E21.693, For vertical channel (EPO)257/E27.086, Storage electrode stacked over the transistor257/E27.091, Transistor in trench (EPO)257/E27.096, Vertical transistor (EPO)257/E27.103, Electrically programmable ROM (EPO)438/257Having additional gate electrode surrounded by dielectric (i.e., floating gate)ExaminersPrimary: Chaudhuri, OlikAssistant: Weiss, Howard Attorney, Agent or FirmForeign Patent References
International ClassesH01L 027/108H01L 029/76 H01L 029/94 H01L 029/788 AbstractA densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the bitlines. The array also has vertical pillars, each having a channel formed between source and drain regions. Two transistors are formed per pillar. This is achieved by forming two gates per pillar formed on opposite pillar sidewalls which are along the bitline direction. This forms two wordlines or gates per pillar arranged in the wordline direction. The source regions are self-aligned and located below the pillars. The source regions of adjacent bit lines are isolated from each other without increasing the cell size. Two floating gates per pillar may be used for EEPROM or flash memory application. The isolated sources allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. For Gbit DRAM applications, stack or trench capacitors may be formed on the pillars, or in trenches surrounding the pillars, respectively. When two capacitors or two floating gates are formed per pillar, the effective memory cell size is 1 bit/2F2.Other References
Field of SearchInsulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell)Vertical transistor Stacked capacitor With additional contacted control electrode Gate electrode in groove Mesa structure (e.g., including undercut or stepped mesa configuration or having constant slope taper) Having additional gate electrode surrounded by dielectric (i.e., floating gate) Including forming gate electrode in trench or recess in substrate Tunneling insulator | |
