Method and apparatus for maintaining transaction ordering and supporting deferred replies in a bus bridge
Delayed transaction protocol for computer system bus
Providing data from a bridge to a requesting device while the bridge is receiving the data
Bus to bus bridge deadlock prevention system Patent #: 5889972
ApplicationNo. 995386 filed on 12/22/1997
US Classes:710/312, Multiple bridges370/402, Bridge between bus systems710/107Bus access regulation
ExaminersPrimary: Ray, Gopal C.
Attorney, Agent or Firm
International ClassesG06F 013/00
AbstractA PCI bridge is configured to perform delayed read operations in response to a memory read initiated on the PCI bus. Normally, the PCI bridge is configured to discard delayed read data read from main memory following a predetermined discard count time after the PCI master establishing the delayed read operation is retried on the PCI bus. The computer system further includes a secondary bus bridge such as an ISA bridge for providing an interface between the PCI bus and an ISA bus. When an ISA device desires to read data from the main memory, the ISA bridge asserts a flush request signal. The PCI bridge responsively flushes any pending CPU to PCI transactions pending within the PCI bridge. When the flushing operation is complete, the PCI bridge asserts an acknowledge signal. A PCI arbiter for arbitrating ownership of the PCI bus may increase a level of arbitration priority provided to the ISA bridge in response to assertion of the acknowledge signal. The PCI bridge is advantageously configured to decrease the time associated with discarding of the delayed read data when the acknowledge signal is asserted.