Test access port controller and a method of effecting communication using the same
October 29, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesIntermodule test across system bus utilizing serial test bus Boundary scan architecture extension IEEE Std. 1149.1 boundary scan circuit capable of built-in self-testing Architecture for system-wide standardized intra-module and inter-module fault testing Test systems for obtaining a sample-on-the-fly event trace for an integrated circuit with an integrated debug trigger apparatus and an external pulse pin Diagnostic memory access Patent #: 5781558 InventorApplicationNo. 960007 filed on 10/29/1997US Classes:714/727, Boundary scan365/201TestingExaminersPrimary: Beausoliel, Robert W. Jr.Assistant: Iqbal, Nadeem Attorney, Agent or FirmForeign Patent References
International ClassG01R 031/28Foreign Application Priority Data1996-10-31 GBAbstractThere is disclosed a test access port controller for effecting communications across a chip boundary having a test mode and a diagnostic mode of operation, wherein in the test mode of operation the test data is resultant data from a test operation having an expected and time delayed relationship, and in the diagnostic mode of operation diagnostic data is conveyed both on and off chip in the form of respective independent input and output serial bit streams simultaneously through the test access port controller.Other References
Field of SearchFault locating (i.e., diagnosis or testing)Particular access structure Built-in hardware for diagnosing or testing within-system component (e.g., microprocessor test mode circuit, scan path) Scan path testing (e.g., level sensitive scan design (LSSD)) Boundary scan Plural scan paths Built-in testing circuit (BILBO) | |
