Differential switched-capacitor sigma-delta modulator
Multistage bandpass Ɗ Σ modulators and analog-to-digital converters
Sigma delta modulator
Bandpass sigma delta converter suitable for multiple protocols
Radio receiver for mobile reception with sampling rate oscillator frequency being an integer-number multiple of reference oscillation frequency
Time division multiplex transmitting/receiving system
Switched-capacitor integrator with chopper stabilization performed at the sampling rate
Analog-to-digital converters using multistage bandpass delta sigma modulators with arbitrary center frequency
Phase detecting method and phase detector and FM receiver using phase detecting method
ApplicationNo. 928874 filed on 09/12/1997
US Classes:341/143Differential encoder and/or decoder (e.g., delta modulation, differential pulse code modulation)
ExaminersPrimary: Williams, Howard L.
Attorney, Agent or Firm
Foreign Patent References
International ClassH03M 003/00
AbstractA bandpass ΣƊ DC utilizing either a single-loop or a MASH architecture wherein the resonators are implemented as either a delay cell resonator, a delay cell based resonator, a Forward-Euler resonator, or a two-path interleaved resonator. The resonator can be synthesized with analog circuit techniques such as active-RC, gm-C, MOSFET-C, switched capacitor, or switched current. The switched capacitor or switched current circuits can be designed using single-sampling, double-sampling, or multi-sampling circuits. The non-stringent requirement of a ΣƊ ADC using switched capacitor circuits allows the ADC to be implemented in a CMOS process to minimize cost and reduce power consumption. Double-sampling circuits provide improved matching and improved tolerance to sampling clock jitter. In particular, a bandpass MASH 4-4 ΣƊ ADC provides a simulated signal-to-noise ratio of 85 dB at an oversampling ratio of 32 for a CDMA application. The bandpass ΣƊ ADC can also be used in conjunction with undersampling to provide a frequency downconversion.