Programmable logic device architectures

Patent 5982195 Issued on November 9, 1999. Estimated Expiration Date:

June 11, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Re34363

3473160

Programmable logic array device using EPROM technology
Patent #: 4609986
Issued on: 09/02/1986
Inventor: Hartmann , et al.

Programmable logic array device using EPROM technology
Patent #: 4617479
Issued on: 10/14/1986
Inventor: Hartmann , et al.

Special interconnect for configurable logic array
Patent #: 4642487
Issued on: 02/10/1987
Inventor: Carter

Programmable logic storage element for programmable logic devices
Patent #: 4677318
Issued on: 06/30/1987
Inventor: Veenstra

Programmable macrocell using eprom or eeprom transistors for architecture control in programmable logic circuits
Patent #: 4713792
Issued on: 12/15/1987
Inventor: Hartmann , et al.

User programmable integrated circuit interconnect architecture and test method
Patent #: 4758745
Issued on: 07/19/1988
Inventor: Elgamal , et al.

Programmable logic array device using EPROM technology
Patent #: 4774421
Issued on: 09/27/1988
Inventor: Hartmann , et al.

Programmable logic device with array blocks connected via programmable interconnect
Patent #: 4871930
Issued on: 10/03/1989
Inventor: Wong , et al.

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Inventors

Application

No. 873169 filed on 06/11/1997

US Classes:

326/41, Significant integrated structure, layout, or layout interconnections326/38, Having details of setting or programming of interconnections or logic functions326/39Array (e.g., PLA, PAL, PLD, etc.)

Examiners

Primary: Tokar, Michael
Assistant: Le, Don Phu

Attorney, Agent or Firm

Fish & Neave, Jackson; Robert R.

Foreign Patent References

454352 A1 EP. 10/13/1991
463746 A2 EP. 01/13/1992
630115 A2 EP. 12/13/1994
WO 95/04404 WO. 02/13/1995
WO 95/22205 WO. 08/13/1995

International Class

H03K 019/177

Abstract

A programmable logic device has regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Horizontal interconnection conductors are associated with each row, and vertical interconnection conductors are associated with each column. Local conductors are interspersed between adjacent pairs of regions in each row for supplying signals to the regions on both sides of the local conductors. Subregions of programmable logic in each region generally have a local output and a global output. The global output is only usable to output to the relatively long-distance horizontal and vertical conductors. The local output is additionally usable as a local feedback and as a local connection to an adjacent region.

Other References

R. C. Minnick, "A Survey of Microcellular Research," Journal of the Association for Computing Machinery, vol. 14, No. 2, pp. 203-241, Apr. 1967
S. E. Wahlstrom, "Programmable Logic Arrays--Cheaper by the Millions," Electronics, Dec. 11, 1967, pp. 90-95
Recent Developments in Switching Theory, A. Mukhopadhyay, ed., Academic Press, New York, 1971, chapters VI and IX, pp. 229-254 and 369-422
The Programmable Gate Array Data Book, 1988, Xilinx, Inc., San Jose, CA
El Gamal et al., "An Architecture for Electrically Configurable Gate Arrays," IEEE Journal of Solid-State Circuits, vol. 24, No. 2, Apr. 1989, pp. 394-398
El-Ayat et al., "A CMOS Electricallyt Configurable Gate Array," IEEE Journal of Solid-State Circuits, vol. 24, No. 3, Jun. 1989, pp. 752-762
ACT Family Field Programmable Gate Array Databook, Apr. 1992, Actel Corporation, Sunnyvale, CA, pp. 1-35 through 1-44
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