Fabrication method for high power MOS device
Power metal-oxide-semiconductor field effect transistor
Insulated gate semiconductor device
Lateral trench MISFET Patent #: 5701026
ApplicationNo. 602150 filed on 02/15/1996
US Classes:257/335, Active channel region has a graded dopant concentration decreasing with distance from source region (e.g., double diffused device, DMOS transistor)257/330, Gate electrode in groove257/341, Plural sections connected in parallel (e.g., power MOSFET)257/E21.418, Vertical power DMOS transistor (EPO)257/E21.419, With recessed gate (EPO)257/E21.42, With recess formed by etching in source/base contact region (EPO)257/E29.257, Having vertical bulk current component or current vertically following trench gate (e.g., vertical power DMOS transistor) (EPO)257/E29.259, With nonplanar surface (EPO)257/E29.26Channel structure lying under slanted or vertical surface or being formed along surface of groove (e.g., trench gate DMOSFET) (EPO)
ExaminersPrimary: Prenty, Mark V.
Attorney, Agent or Firm
International ClassH01L 029/76
Foreign Application Priority Data1995-02-17 JP
AbstractA vertical trench MISFET is provided that includes a semiconductor substrate having a first conductivity type semiconductor, and a second conductivity type impurity layer provided on the first conductivity type semiconductor. A trench extends from a surface of the semiconductor substrate to reach said first conductivity type semiconductor. A second conductivity type base region is formed in a top portion of the semiconductor substrate, and a first conductivity type source region is formed in a part of a surface layer of the second conductivity type base region. A first conductivity type drain drift region having a small thickness is formed in a surface layer of a side wall of the trench. The drain drift region has a higher impurity concentration than a level at which a breakdown voltage measured in a hypothetical diffusion type junction is substantially equal to an element withstand voltage. A gate electrode is formed on an exposed surface of the second conductivity type base region, through a gate insulating film. A source electrode is disposed in contact with surfaces of both of the first conductivity type source region and the second conductivity type base region, while a drain electrode is disposed in contact with a rear surface of the first conductivity type semiconductor.
Field of SearchActive channel region has a graded dopant concentration decreasing with distance from source region (e.g., double diffused device, DMOS transistor)
With means to increase breakdown voltage
Plural sections connected in parallel (e.g., power MOSFET)
Gate controls vertical charge flow portion of channel (e.g., VMOS device)
Gate electrode in groove