Method for forming high capacitance memory cells
May 29, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of forming a trench capacitor on a semiconductor substrate High density DRAM Dram cell formed on an insulating layer having a buried semiconductor pillar structure and a manufacturing method thereof Dram with a vertical capacitor and transistor High area capacitor formation using dry etching Dynamic RAM having 3-dimensional memory cell structure Method for depositing material on depressions Textured polysilicon stacked trench capacitor Process for fabricating multiple pillars inside a dram trench for increased capacitor surface Self-aligned buried strap for trench type DRAM cells InventorsApplicationNo. 087480 filed on 05/29/1998US Classes:438/386, Trench capacitor438/243, Trench capacitor438/398Including texturizing storage node layerExaminersPrimary: Nguyen, Tan T.Attorney, Agent or FirmInternational ClassH01L 021/20AbstractA method and structure for high capacitance memory cells is provided. The method includes forming a trench capacitor in a semiconductor substrate. A self-structured mask is formed on the interior surface of the trench. The interior surface of the trench is etched to form an array of silicon pillars. The self-structured mask is removed. Then an insulator layer is formed on the array of silicon pillars. A polycrystalline semiconductor plate extends outwardly from the insulator layer in the trench.Other References
Field of SearchTrench capacitorHaving stacked capacitor structure (e.g., stacked trench, buried stacked capacitor, etc.) Including isolation means formed in trench Stacked capacitor Including texturizing storage node layer Trench capacitor Utilizing stacked capacitor structure (e.g., stacked trench, buried stacked capacitor, etc.) Including isolation means formed in trench Stacked capacitor Including texturizing storage node layer | |
