Parallel pipelined instruction processing system for very long instruction word
Decoded instruction cache architecture with each instruction field in multiple-instruction cache line directly connected to specific functional unit
VLIW processor which uses path information generated by a branch control unit to inhibit operations which are not on a correct path
Software scheduled superscalar computer architecture
Scaleable very long instruction word processor with parallelism matching
Variable word length very long instruction word instruction processor with word length register or instruction number register Patent #: 5774737
ApplicationNo. 998486 filed on 12/29/1997
US Classes:712/215, Simultaneous issuance of multiple instructions712/24Long instruction word
ExaminersPrimary: Vu, Viet D.
Attorney, Agent or Firm
International ClassG06F 009/38
AbstractA very long instruction word (VLIW) architecture describes a processor comprising multiple functional units operating in parallel. A very long instruction word contains a plurality of fields or issue slots for specifying which operations are to be performed by the functional units. Execution of an operation can be inhibited by a guard value specified in the issue slot. Instructions are dispatched in such a guarded VLIW architecture by routing one of a plurality of fields issued for a common functional unit based on the guard value. Thus, an instruction word may contain a greater number of issue slots than there are functional units.