Universal serial bus device controller comprising a FIFO associated with a plurality of endpoints and a memory for storing an identifier of a current endpoint
August 12, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesApparatus for establishing multi-address and conference call connections Adaptive digital network interface Methods and apparatus for performing restricted token operations on an FDDI network Interprocess communications control system Shared buffer switching module Selective call receiver with computer interface message notification FA controller and data processing method therefor Data-packet fifo buffer system with end-of-packet flags Patent #: 5860119 InventorApplicationNo. 909988 filed on 08/12/1997US Classes:710/53, Alternately filling or emptying buffers710/4, Address data transfer710/52Input/Output data bufferingExaminersPrimary: Lee, Thomas C.Assistant: Yuan, Chien Attorney, Agent or FirmInternational ClassG06F 013/14AbstractA versatile USB controller comprises a serial interface engine (SIE) for connection with a host. The SIE is capable of simulating a disconnect/connect sequence in situations where a reboot of the device is appropriate. The controller further includes a control store for keeping track of multiple endpoints of a device. A FIFO provides data transfer between each of the endpoints and the host. A state machine provides transaction sequencing with the host for each endpoint. In a variation of the preferred embodiment, a second FIFO is included to provide additional buffering capability.Other References
| |
