Ultra high density flash memory having vertically stacked devices
August 20, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesStacked capacitor doping technique making use of rugged polysilicon Method of making stacked E-cell capacitor DRAM cell High density data storage using stacked wafers Semiconductor device Method of depositing high density titanium nitride films on semiconductor wafers Fabrication of complementary n-channel and p-channel circuits (ICs) useful in the manufacture of dynamic random access memories (drams) Method of forming a capacitor Use of a high density plasma source having an electrostatic shield for anisotropic polysilicon etching over topography Process for high density flash EPROM cell Method of cleaning high density inductively coupled plasma chamber using capacitive coupling InventorApplicationNo. 915197 filed on 08/20/1997US Classes:257/315, With floating gate electrode257/E21.693, For vertical channel (EPO)257/E27.103, Electrically programmable ROM (EPO)257/E27.112, Including insulator on semiconductor, e.g. SOI (silicon on insulator) (EPO)365/185.03, Multiple values (e.g., analog)365/185.06, Segregated columns438/212Vertical channelExaminersPrimary: Monin, Donald L. Jr.Assistant: Weiss, Howard Attorney, Agent or FirmInternational ClassesH01L 029/788H01L 029/76 G11C 011/34 AbstractAn ultra high density flash EEPROM provides increased nonvolatile storage capacity. A memory array includes densely packed memory cells, each cell having a pillar of semiconductor material that extends outwardly from a working surface of a substrate. The pillar includes source/drain and body regions and has a number of sides. A pair of vertically stacked floating gates is included on at least one of two sides of the pillar. A control gate line also passes through each memory cell. Each memory cell is associated with a control gate line so as to allow selective storage and retrieval of data on the floating gates of the cell. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data, an area of only F2 is needed per bit of data, where F is the minimum lithographic feature size. If multiple charge states (more than two) are used, an area of less than F2 is needed per bit of data.Other References
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