Patent ReferencesCompilers using a universal intermediate language Compilation using two-colored pebbling register allocation method such that spill code amount is invariant with basic block's textual ordering Interprocedural slicing of computer programs using dependence graphs Computer with integrated hierarchical representation (IHR) of program wherein IHR file is available for debugging and optimizing during target execution System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling Method for optimizing computer code to provide more efficient execution on computers having cache memories System and method for solving monotone information propagation problems Patent #: 5327561 InventorAssigneeApplicationNo. 963086 filed on 11/03/1997US Classes:717/156, Using flow graph717/147, Platform-independent form (e.g., abstract code)717/160Including loopExaminersPrimary: Hafiz, Tariq R.Assistant: Ingberg, Todd Attorney, Agent or FirmInternational ClassG06F 009/44AbstractA computer system is directed to convert a program written as a plurality of high level source code modules into corresponding machine executable code. The source code modules are compiled into an object code module, and the object code modules are translated into a single linked code module in the form of a register translation language and logical symbol table compatible with a plurality of computer system hardware architectures. The source code program structures are recovered from the linked code module, and the linked code module is partitioned into a plurality of procedure, and instructions of each of the procedures grouped into basic blocks. A procedure flow graph is constructed for each of the procedures, and a program call graph is constructed for the linked code module. The linked code module is modified by eliminating dead code and moving loop-invariant code from loops. The modified linked code is converted into machine executable code compatible with a target one of said plurality of computer system hardware architectures.Other References
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