Storage access validation to data messages using partial storage address data indexed entries containing permissible address range validation for message source
October 12, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod and apparatus for transaction and identity verification Channel interface circuit with high speed data message header field translation and direct memory access Microprocessor memory management and protection mechanism Virtual memory address translation mechanism with combined hash address table and inverted page table Communications network using IC cards Industrial control communication network and method Separate content addressable memories for storing locked segment addresses and locking processor identifications for controlling access to shared memory Method and apparatus for protecting material on storage media and for transferring material on storage media to various recipients Processor for a programmable controller Method and apparatus for dynamic detection and routing of non-uniform traffic in parallel buffered multistage interconnection networks Inventors
AssigneeApplicationNo. 482618 filed on 06/07/1995US Classes:709/216, Accessing another computer's memory711/152, Memory access blocking711/163Access limitingExaminersPrimary: Kim, Kenneth S.Attorney, Agent or FirmInternational ClassG06F 012/14AbstractA multiprocessor system includes a number of central processing unit (CPUs) and at least one input/output (I/O) device interconnected by routing apparatus for communicating packetized messages therebetween. The messages contain address information identifying the source and destination of the message, and may also contain requests to write to, or read from, storage of a CPU. Protection against errant reads or writes is provided by an access validation method that utilizes access validation information contained in plural entries maintained by each CPU. Each entry provides validation by identifying what elements of the system has read and/or write wccss to the memory of that CPU, without which memory access is denied. | |
