Dielectrically-isolated integrated circuit
Patent 5963785 Issued on October 5, 1999. Estimated Expiration Date: 
February 28, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
February 28, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesEdge barrier of polysilicon and metal for integrated circuit chips Wafer scribe technique using laser by forming polysilicon Patent #: 5543365 InventorsApplicationNo. 808647 filed on 02/28/1997US Classes:438/33, Substrate dicing257/E21.564, SOI together with lateral isolation, e.g., using local oxidation of silicon, or dielectric or polycrystalline material refilled trench or air gap isolation regions, e.g., completely isolated semiconductor islands (EPO)257/E21.703, Substrate is semiconductor body (EPO)257/E27.112, Including insulator on semiconductor, e.g. SOI (silicon on insulator) (EPO)438/68, Substrate dicing438/114, Utilizing a coating to perfect the dicing438/458, Subsequent separation into plural bodies (e.g., delaminating, dicing, etc.)438/460, SEMICONDUCTOR SUBSTRATE DICING438/465Having a perfecting coatingExaminersPrimary: Graybill, David E.Attorney, Agent or FirmInternational ClassH01L 021/302Foreign Application Priority Data1996-02-29 JPAbstractIn a semiconductor integrated circuit consisting of a plurality of semiconductor chips each having a plurality of islands, two or more bonding wires each having different potential are connected to bonding pads formed on the surface of semiconductor chips. The islands are isolated by a dielectric isolation region comprising polysilicon film and isolation film formed in an isolation groove. The polysilicon film is exposed at a dicing line region around the semiconductor chip and a surface of the polysilicon film is made highly resistive. If two or more bonding wires come into contact with the polysilicon film exposed at a peripheral region of the semiconductor chip to cause short circuit, parasitic conductance does not occur between two or more bonding wires because the peripheral region of the semiconductor chip has high resistivity, whereby variation in characteristics of the semiconductor integrated circuit can be suppressed.Field of SearchSubstrate dicingSubstrate dicing Substrate dicing Utilizing a coating to perfect the dicing Subsequent separation into plural bodies (e.g., delaminating, dicing, etc.) SEMICONDUCTOR SUBSTRATE DICING Beam lead formation Having specified scribe region structure (e.g., alignment mark, plural grooves, etc.) By electromagnetic irradiation (e.g., electron, laser, etc.) With attachment to temporary support or carrier Having a perfecting coating | |
