Highly compact EPROM and flash EEPROM devices

Patent 5963480 Issued on October 5, 1999. Estimated Expiration Date:

November 12, 2018. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Fault-tolerant cell addressable array
Patent #: 4051354
Issued on: 09/27/1977
Inventor: Choate

Memory field effect storage device
Patent #: 4087795
Issued on: 05/02/1978
Inventor: Rossler

Memory sparing arrangement
Patent #: 4093985
Issued on: 06/06/1978
Inventor: Das

Acquisition and storage of analog signals
Patent #: 4181980
Issued on: 01/01/1980
Inventor: McCoy

Word-by-word electrically reprogrammable nonvolatile memory
Patent #: 4279024
Issued on: 07/14/1981
Inventor: Schrenk

Multiple bit read-only memory cell and its sense amplifier
Patent #: 4287570
Issued on: 09/01/1981
Inventor: Stark

Method of programming an electrically alterable nonvolatile memory
Patent #: 4357685
Issued on: 11/02/1982
Inventor: Daniele , et al.

Memory array with redundant elements
Patent #: 4422161
Issued on: 12/20/1983
Inventor: Kressel , et al.

Storage element reconfiguration
Patent #: 4430727
Issued on: 02/07/1984
Inventor: Moore , et al.

Highly scalable dynamic RAM cell with self-signal amplification
Patent #: 4448400
Issued on: 05/15/1984
Inventor: Harari

More ...

Inventor

Harari, Eliyahou

Application

No. 190648 filed on 11/12/1998

US Classes:

365/185.29, Erase257/E21.179, Floating or plural gate structure (EPO)257/E21.68, Electrically programmable (EPROM), i.e., floating gate memory structures (EPO)257/E27.103, Electrically programmable ROM (EPO)257/E29.302, Hi-lo programming levels only (EPO)257/E29.306, Hot carrier injection from channel (EPO)365/185.09, Error correction (e.g., redundancy, endurance)365/185.3, Over erasure365/185.33, Flash365/200, Bad bit365/218, Erase365/230.03, Plural blocks or banks365/236Counting

Examiners

Primary: Nguyen, Viet Q.

Attorney, Agent or Firm

Majestic, Parsons, Siebert & Hsue

Foreign Patent References

0251889 EP. 01/20/1988
0349775 EP. 10/20/1990
2430065 FR. 02/20/1980
3200872 DE. 07/20/1983
54-158141 JP. 12/20/1979
58-215795 JP. 04/20/1983
58-086777 JP. 05/20/1983
58-215794 JP. 06/20/1983
58-215795 JP. 08/20/1983
59-162695 JP. 01/20/1984
59-45695 JP. 09/20/1984
60-076097 JP. 04/20/1985
62-283496 JP. 03/20/1987
62-283496 JP. 05/20/1987
62-283497 JP. 11/20/1987
63-183700 JP. 01/20/1988
63-200398 JP. 08/20/1988
58-060493 JP. 04/20/1993
2215155 GB. 09/20/1989

International Class

G11C 007/00

Abstract

Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

Other References

M. Stark, "Two Bits Per Cell ROM", Digest of Papers VLSI, 1981, pp. 209-212
Torelli et al., "An Improved Method for Programming a Word-Erasable EEPROM," Alta Frequenza, vol. 52, No. 5, Nov. 1983, pp. 487-494
Harold, "Production of E.P.R.O.M. Loading," New Electronics, vol. 15, No. 3, Feb. 1982, pp. 47-50
Torelli, "An LSI Technology Fully Compatible EAROM Cell," Alta Frequenza, No. 6, vol. LI, pp. 345-351 (1982)
Lucerno et al., "A 16kbit Smart 5 V-Only EEPROM with Redundancy", IEEE Journal of Solid State Circuits, vol. SC-18, No. 5, pp. 539544 Oct. 1983
Berenga et al., "E2-PROM TV Synthesizer," 1978 IEEE ISSCC Digest of Technical Papers, Sec 039463, pp. 196-197, Feb. 1978
"Japanese Develop Nondestructive Analog Semiconductor Memory," Electronics Review, Jul. 11, 1974, p. 29
Alberts et al., Multi-Bit Storage FET EAROM Cell, IBM Technical Disclosure Buletin, vol. 24, No. 7A, Dec. 1981, p. 3311
Horiguchi et al., An Experimental Large-Capacity Semiconductor File Memory Using 16-Levels/Cell Storage', IEEE Journal of Solid-State Circuits, Feb. 1988, p. 27-33
Bleiker et al., "A Four-State EEPROM Using Floating-Gate Memory Cells," IEEE Journal of Solid-State Circuits, Jul. 1987, p. 460-463
Furuyama et al., "An Experimental 2 Bit/Cell Storage DRAM for Macrocell or Memory-on-Logic Applications," IEEE Custom Integrated Circuits Conference, May 1988, p. 4.4.