Configurable logic element with fast feedback paths

Patent 5963050 Issued on October 5, 1999. Estimated Expiration Date:

March 24, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

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Inventors

Application

No. 823265 filed on 03/24/1997

US Classes:

326/41, Significant integrated structure, layout, or layout interconnections326/37, MULTIFUNCTIONAL OR PROGRAMMABLE (E.G., UNIVERSAL, ETC.)326/39Array (e.g., PLA, PAL, PLD, etc.)

Examiners

Primary: Tokar, Michael
Assistant: Tran, Andrew Q.

Attorney, Agent or Firm

Cartier; Lois D., Young; Edel M.

Foreign Patent References

0461798A2 EP. 06/13/1991
0748049A2 EP. 12/13/1996
0746107A2 EP. 12/13/1996
2300951 GB. 11/13/1996
WO9410754 WO. 05/13/1994

International Class

H01L 025/00

Abstract

The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. Each tile comprises a logic block that includes a Configurable Logic Element (CLE) and an output multiplexer. Fast feedback paths are provided within the logic block to connect the CLE outputs to the CLE inputs, either directly or through an input multiplexer. The fast feedback paths bypass the output multiplexer and therefore provide faster feedback than can be obtained in most conventional FPGA logic blocks. In one embodiment, the fast feedback paths provide the ability for all function generators in one CLE to drive each other through fast feedback paths, regardless of how logic is mapped into the function generators of the CLE.

Other References

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